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Philips Semiconductors
Product specification
TrenchMOSTM transistor Logic level FET
GENERAL DESCRIPTION
N-channel enhancement mode logic level field-effect power transistor in a plastic envelope suitable for surface mounting Using 'trench' technology the device features very low on-state resistance and has integral zener diodes giving ESD protection up to 2kV. It is intended for use in DC-DC converters and general purpose switching applications.
PHB125N06LT
QUICK REFERENCE DATA
SYMBOL VDS ID Ptot Tj RDS(ON) PARAMETER Drain-source voltage Drain current (DC)1 Total power dissipation Junction temperature Drain-source on-state resistance VGS = 5 V MAX. 55 75 250 175 8 UNIT V A W C m
PINNING - SOT404
PIN 1 2 3 mb gate drain source drain DESCRIPTION
PIN CONFIGURATION
mb
SYMBOL
d
g
2 1 3
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL VDS VDGR VGS ID ID IDM Ptot Tstg, Tj PARAMETER Drain-source voltage Drain-gate voltage Gate-source voltage Drain current (DC)1 Drain current (DC)1 Drain current (pulse peak value) Total power dissipation Storage & operating temperature CONDITIONS RGS = 20 k Tmb = 25 C Tmb = 100 C Tmb = 25 C Tmb = 25 C MIN. - 55 MAX. 55 55 10 75 75 240 250 175 UNIT V V V A A A W C
ESD LIMITING VALUE
SYMBOL VC PARAMETER Electrostatic discharge capacitor voltage CONDITIONS Human body model (100 pF, 1.5 k) MIN. MAX. 2 UNIT kV
1 Current limited by package to 75A from a theoretical value of 125A. December 1997 1 Rev 1.100
Philips Semiconductors
Product specification
TrenchMOSTM transistor Logic level FET
THERMAL RESISTANCES
SYMBOL Rth j-mb Rth j-a PARAMETER Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS Minimum footprint,FR4 board TYP. 50
PHB125N06LT
MAX. 0.6 -
UNIT K/W K/W
STATIC CHARACTERISTICS
Tj= 25C unless otherwise specified SYMBOL V(BR)DSS VGS(TO) IDSS IGSS V(BR)GSS RDS(ON) PARAMETER Drain-source breakdown voltage Gate threshold voltage Zero gate voltage drain current Gate source leakage current Gate-source breakdown voltage Drain-source on-state resistance CONDITIONS VGS = 0 V; ID = 0.25 mA; Tj = -55C VDS = VGS; ID = 1 mA Tj = 175C Tj = -55C VDS = 55 V; VGS = 0 V; VGS = 5 V; VDS = 0 V IG = 1 mA; VGS = 5 V; ID = 25 A Tj = 175C Tj = 175C Tj = 175C MIN. 55 50 1.0 0.5 10 TYP. 1.5 0.05 0.02 6.5 MAX. 2.0 2.3 10 500 1 10 8 17 UNIT V V V V V A uA A A V m m
DYNAMIC CHARACTERISTICS
Tmb = 25C unless otherwise specified SYMBOL gfs Qg(tot) Qgs Qgd Ciss Coss Crss td on tr td off tf Ld Ls PARAMETER Forward transconductance Total gate charge Gate-source charge Gate-drain (Miller) charge Input capacitance Output capacitance Feedback capacitance Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal source inductance CONDITIONS VDS = 25 V; ID = 25 A ID = 50 A; VDD = 44 V; VGS = 5 V MIN. 40 TYP. 90 84 18 39 5200 840 350 45 120 225 100 3.5 7.5 MAX. 6900 1000 480 60 170 300 135 UNIT S nC nC nC pF pF pF ns ns ns ns nH nH
VGS = 0 V; VDS = 25 V; f = 1 MHz
VDD = 30 V; ID = 25 A; VGS = 5 V; RG = 10
Measured from upper edge of drain tab to centre of die Measured from source lead soldering point to source bond pad
December 1997
2
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOSTM transistor Logic level FET
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25C unless otherwise specified SYMBOL IDR IDRM VSD trr Qrr PARAMETER Continuous reverse drain current Pulsed reverse drain current Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS MIN. IF = 25 A; VGS = 0 V IF = 75 A; VGS = 0 V IF = 75 A; -dIF/dt = 100 A/s; VGS = -10 V; VR = 30 V -
PHB125N06LT
TYP. 0.85 1.0 65 0.18
MAX. 75 240 1.2 -
UNIT A A V V ns C
AVALANCHE LIMITING VALUE
SYMBOL WDSS PARAMETER Drain-source non-repetitive unclamped inductive turn-off energy CONDITIONS ID = 75 A; VDD 25 V; VGS = 5 V; RGS = 50 ; Tmb = 25 C MIN. TYP. MAX. 500 UNIT mJ
December 1997
3
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOSTM transistor Logic level FET
PHB125N06LT
120 110 100 90 80 70 60 50 40 30 20 10 0
PD%
Normalised Power Derating
1E+00
Zth / (K/W)
0.5 1E-01 0.2 0.1 0.05 1E-02 0.02 0 1E-03 1E-07
P D
tp
D=
tp T t
T
0
20
40
60
80 100 Tmb / C
120
140
160
180
1E-05
1E-03 t/s
1E-01
1E+01
Fig.1. Normalised power dissipation. PD% = 100PD/PD 25 C = f(Tmb)
ID (A) Current Derating
100 10 ID/A 80
Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T
150 125
3.4 4.0
VGS/V =
3.2
Limited by package
100
60 3.0
75
2.8
50 25 0 0 20 40 60 80 100 Tmb / C 120 140 160 180
40 2.6 20 2.4 2.2 0 0 2 4 VDS/V 6 8 10
Fig.2. Normalised continuous drain current. ID% = 100ID/ID 25 C = f(Tmb); conditions: VGS 5 V
Fig.5. Typical output characteristics, Tj = 25 C. ID = f(VDS); parameter VGS
RDS(ON) / mOhm VGS / V = 3 3.2
BUK9508-55
BUKX508-55
1000
ID / A
15
3.4 3.6
RDS(ON) = VDS/ID 100
tp = 10 us 100 us 1 ms
10 4 5 5
10
DC
10 ms 100 ms
0
1
1
10
VDS / V
100
0
20
40
60 ID / A
80
100
120
Fig.3. Safe operating area. Tmb = 25 C ID & IDM = f(VDS); IDM single pulse; parameter tp
Fig.6. Typical on-state resistance, Tj = 25 C. RDS(ON) = f(ID); parameter VGS
December 1997
4
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOSTM transistor Logic level FET
PHB125N06LT
100 ID/A 80
2.5
VGS(TO) / V max.
BUK959-60
2 typ.
60
1.5 min.
40 Tj/C = 20 175 25
1
0.5
0
0
1
VGS/V
2
3
4
0 -100
-50
0
50 Tj / C
100
150
200
Fig.7. Typical transfer characteristics. ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj
120 gfs/S 110 100 90 80 70 60 50 40 30 20 10 0 0 20 40 ID/A 60 80 100
Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
Sub-Threshold Conduction
1E-01
1E-02 2% typ 98%
1E-03
1E-04
1E-05
1E-05
0
0.5
1
1.5
2
2.5
3
Fig.8. Typical transconductance, Tj = 25 C. gfs = f(ID); conditions: VDS = 25 V
BUK959-60
Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 C; VDS = VGS
12
2.5
a
Rds(on) normlised to 25degC
10
2
1.5
Thousands (pF)
8
6
Ciss
4
1
2
0.5 -100 -50 0 50 Tmb / degC 100 150 200
0 0.01
0.1
1 VDS/V
10
Coss Crss 100
Fig.9. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 C = f(Tj); ID = 25 A; VGS = 5 V
Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
December 1997
5
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOSTM transistor Logic level FET
PHB125N06LT
6 VGS/V 5 VDS = 14V VDS = 44V
120 110 100 90 80 70 60 50 40 30 20 10 0
0 10 20 30 40 50 60 QG/nC 70 80 90
WDSS%
4
3
2
1
0
20
40
60
80
100 120 Tmb / C
140
160
180
Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG); conditions: ID = 50 A; parameter VDS
100 IF/A 80
Fig.15. Normalised avalanche energy rating. WDSS% = f(Tmb); conditions: ID = 75 A
+
L VDS
VDD
60 Tj/C = 40 175 25
VGS 0 T.U.T.
-ID/100
20
RGS
R 01 shunt
0
0
0.2
0.4
0.6 VSDS/V
0.8
1
1.2
Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
Fig.16. Avalanche energy test circuit. 2 WDSS = 0.5 LID BVDSS /(BVDSS - VDD )
+
RD VDS VGS 0 RG T.U.T.
VDD
-
Fig.17. Switching test circuit.
December 1997
6
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOSTM transistor Logic level FET
MECHANICAL DATA
Dimensions in mm Net Mass: 1.4 g
10.3 max 4.5 max 1.4 max
PHB125N06LT
11 max 15.4
2.5 0.85 max (x2) 2.54 (x2)
0.5
Fig.18. SOT404 : centre pin connected to mounting base.
MOUNTING INSTRUCTIONS
Dimensions in mm
11.5
9.0
17.5 2.0
3.8
5.08
Fig.19. SOT404 : soldering pattern for surface mounting.
Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Epoxy meets UL94 V0 at 1/8".
December 1997
7
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOSTM transistor Logic level FET
DEFINITIONS
Data sheet status Objective specification Product specification Limiting values
PHB125N06LT
This data sheet contains target or goal specifications for product development. This data sheet contains final product specifications.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. (c) Philips Electronics N.V. 1997 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
December 1997
8
Rev 1.100

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